1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of erasing stored information from the nonvolatile semiconductor device, and more particularly, to a nonvolatile semiconductor memory device such as EEPROMs (Electrically Erasable and Programmable Read Only Memory) capable of electrically erasing stored information and a method of erasing stored information thereof.
2. Description of the Related Art
As one of the nonvolatile semiconductor memory devices, EEPROMs have been known. In the EEPROM, information can be electrically written and read out, and the feature may be to erase electrically stored information.
In order to erase the electrically stored information, a charge carrier stored in a floating gate must be removed, using a tunneling phenomenon (this tunnelling phenomenon has been known as, especially, the Fowler Nordheim tunnelling phenomenon) of a thin insulating film. According to a conventional erasing method, a high voltage is applied to a source or drain region provided in a semiconductor substrate to render a high electric field to the floating gate. As a result, a charge carrier (electrons in this case) stored in the floating gate is removed to the source or drain region through a gate insulating film. However, since the charge carrier is removed to the source or drain region provided in the substrate, a large number of electrons or holes are generated at the interface between the gate insulating film and the source or drain region, so that an excess source or drain current flows therethrough during erasing.
The problem of the excess current flowing through the source or drain region during erasing of the stored information will be described below with reference to accompanying drawings, using a memory cell of EEPROM, comprised of a p-type semiconductor substrate and n-type source and drain regions, as a model.
Prior to the description of the excess current, a structure of an EEPROM shown in FIG. 7 will be explained. An n-type drain region 702 and an n-type source region 703 are provided in a p-type semiconductor substrate 701. A floating gate 705, a part of which extends to the drain region 702, is disposed through a first gate insulating film 704 above a channel region which is defined between these n-type regions 702 and 703. A control gate 707 is provided above the floating gate through an interlevel insulator 706. A side wall insulating film 708 is provided on a side wall of a stacked gate constituted by these gates, and a second gate insulating film 709 integrally formed with the side wall insulating film is provided on the channel region. A select gate 710 is provided on both the second gate insulating film 709 and the side wall insulating film 708.
FIG. 7 shows a state wherein a voltage is applied during erasing to the memory cell of the EEPROM having the above structure. That is, a high voltage is applied to the n-type drain region 702 (reference numeral 711 in FIG. 7 denotes a depletion layer). As a result, electrons 712 (charge carrier) stored in the floating gate 705 are removed through the first gate insulating film 704 to the n-type drain region 702 provided in the substrate 701. At this time, a large number of electrons and holes are generated at the interface between the first gate insulating film 704 and the n-type drain region 702 to cause an increase in drain current. That is, the excess drain current may bring about.
The generation of a large number of electrons and holes will be described in detail with reference to an energy band diagram shown in FIG. 8.
A region represented by reference numeral 801 in the drawing is a region corresponding to the floating gate 705 shown in FIG. 7, reference numeral 802 denotes a region corresponding to the first gate insulating film 704 shown in FIG. 7, and reference numeral 803 denotes a region corresponding to the n-type drain region 702 shown in FIG. 7. In addition, reference numeral 804 denotes a conduction band of a semiconductor (e.g., silicon), and reference numeral 805 denotes a valence band thereof. FIG. 8 shows a state wherein a high voltage is applied to the n-type drain region 702, i.e., the region 803 in FIG. 8. When the high voltage is applied to the n-type drain region 702, the band which is present in the region 803 in FIG. 8 is bent, so that the width of the forbidden band 806 located near the first gate insulating film 704 (e.g., silicon oxide) is decreased. When the width of the forbidden band 806 is decreased, electrons 715 which are present in the valence band 805 are transferred to the conduction band 804 by a tunnelling phenomenon, whereby, so-called the band-to-band tunnelling occurs. Holes 714 are left in the valence band 805. The electrons 715 flow through the n-type drain region 702, i.e., a high potential power supply, and the holes 714 flow through the substrate 701, i.e., a low potential power supply such as the ground, thereby causing an increase in the drain current.
In the conventional erasing method described above, since the charge carrier stored in the floating gate 705 is removed by applying the high voltage to the region (e.g., n-type drain region 702) provided in the substrate 701 connected to the low voltage power supply, the problem of the excess current generated by the band-to-band tunnelling cannot be avoided. As described above, when the excess current is generated during erasing, an electric potential cannot be satisfactorily applied to the device by using an internal step-up means such as charge pumping circuits thereby bringing about unwanted voltage drop. Therefore, various problems such as undesired delay of the erasing time, unsatisfactory removal of the charge carrier, etc., may occur. That is, in the conventional EEPROM, it is difficult to perform the erase operation by the internal step-up means.